1. Field of the Invention
The present invention relates to a microcomputer for executing instructions in accordance with a microprogram system and having a function to control generation of a refresh cycle for a dynamic RAM (hereinafter referred to as "DRAM").
2. Description of the Prior Art
A constituent element of a microcomputer which fetches, interprets and executes instructions from outside is referred to as "CPU", and an entire apparatus including this CPU and a DRAM refresh controller as "microcomputer" hereinafter.
The CPU receives and supplies data through a data bus under the control of a bus interface control unit provided herein in order to fetch instructions and read and write data. The DRAM also uses the data bus under the control of a different bus interface control unit during a refresh cycle. Since there exist both the bus interface control unit of the CPU and the bus interface control unit of the DRAM refresh controller, the microcomputer requires an arbitration control unit for arbitrating the use of the data bus between the CPU and the DRAM refresh controller.
FIG. 6 is a block diagram of a microcomputer including a conventional DRAM refresh controller and an external memory formed with DRAM. In FIG.6, reference numeral 1 represents a DRAM refresh controller, 2 a CPU, and 3 a microcomputer. Numeral 4 represents an internal data bus in the microcomputer 3, 5 a bus arbiter for arbitrating the use of the bus between the DRAM refresh controller 1 and the CPU 2, 6 a data bus input and output unit connected between the internal data bus 4 and the external data bus 7 of the microcomputer 3, 8 an external memory subsystem composed of DRAM connected to the external data bus 7, 9 a refresh timer in the DRAM refresh controller 1 for counting the interval of a DRAM refresh cycle and generating a terminal count signal when it finishes counting, and 10 a bus interface control unit in the DRAM refresh controller 1 responsive to the terminal count signal of the refresh timer to control the use of the internal data bus 4. Numeral 11 designates the terminal count signal indicating the time to refresh the DRAM after the termination of the count operation of the refresh timer, 12 a signal indicating a request that the DRAM refresh controller 1 use the internal data bus 4 for refreshing the memory subsystem 8, which is a bus access request signal to be applied to the bus arbiter 5, 13 a bus access permit signal indicating permission for the CPU 2 to use the internal data bus 4, 14 a control storage unit for storing a set of microinstructions specifying the internal operation of the CPU 2, 15 a microinstruction sequencer as means for controlling the order of executing a set of microinstructions stored in the control storage unit 14 by specifying an address, 16 an instruction execution unit for executing the instructions of the CPU 2 under the control of contents of the microinstructions output from the control storage unit 14, 17 a bus interface control unit in the CPU 2, connected between the instruction execution unit 16 and the internal data bus 4 for controlling the use of the internal data bus 4 by the CPU 2, and 18 a bus request signal indicating a request issued by the instruction execution unit 16 to the bus interface control unit 17 when the CPU 2 is to use the internal data bus 4 for reading and writing data for the execution of instructions.
A description will subsequently be given of the operation of the microcomputer with reference to FIG.6. The operation of the microcomputer when the memory subsystem 8 composed of a DRAM does not need to be refreshed will first be described. The refresh timer 9 continues counting until the refresh operation is needed, and the terminal count signal 11 is inactive (invalid). Therefore, the bus interface control unit 10 in the DRAM refresh controller 1 keeps the bus access request signal 12 inactive with respect to the bus arbiter 5. For this reason, the bus arbiter 5 continues to generate to the CPU 2 the bus access permit signal 13 indicating that the CPU 2 may use the internal data bus 4.
Meanwhile, the CPU 2 may access the memory subsystem 8 through the internal data bus 4 to execute instructions in some cases. The CPU 2 reads microinstructions from the control storage unit 14 in the order controlled by the microinstruction sequencer 15. When it is necessary to read and write data, the microinstructions notify the instruction execution unit 16 of this. Then the instruction execution unit 16 activates the bus request signal 18 and notifies the bus interface control unit 17 that the CPU 2 needs to use the internal data bus 4. Since the bus access permit signal 13 is active, the bus interface control unit 17 can respond to the bus request signal 18, that is, a bus access request from the instruction execution unit 16. Therefore, the bus interface control unit 17 uses the internal data bus 4 to read data from and write data to the memory subsystem 8 through the data bus input and output unit 6 and the external data bus 7.
A description will subsequently be given of the operation of the microcomputer when the memory subsystem 8 composed of a DRAM needs to be refreshed. Generally speaking, the operation of refreshing the DRAM needs to be executed first before any other operation. Therefore, in this case, the use of the internal data bus 4 for refreshing the DRAM comes prior to the use of the internal data bus 4 by the CPU 2 for reading and writing data.
The refresh timer 9 counts the time for refreshing the memory subsystem 8. The refresh timer 9 activates the count signal 11 when there is an overflow (or an underflow when it counts backwards), and notifies the bus interface control unit 10 that it is time to refresh the memory subsystem 8. At this time, the bus interface control unit 10 activates the bus access request signal 12 and notifies the bus arbiter 5 that the top priority should be given to the use the internal data bus 4 for refreshing. Thereby, the bus arbiter 5 makes the bus access permit signal 13 inactive to the CPU 2 and notifies the CPU 2 that the CPU 2 cannot use the internal data bus 4.
With the above operation flow, access to the internal data bus 4 is shifted to the DRAM refresh controller 1, whereby the bus interface control unit 10 uses the internal data bus 4 to refresh the memory subsystem 8 through the data bus input and output unit 6 and the external data bus 7.
A description will subsequently he given of the operation of the microcomputer when the CPU 2 needs to use the internal data bus 4 during the above-described refresh cycle. The operation of the microcomputer until the CPU 2 activates the bus request signal 18 is perfectly identical to the case where the memory subsystem 8 does not need to be refreshed. Since the bus arbiter 5 keeps the bus access permit signal 13 inactive during the refresh cycle, the bus interface control unit 17 cannot allow the instruction execution unit 16 to read and write data and waits for the bus access permit signal 13 to become active again. Therefore, the CPU 2 (instruction execution unit 16) cannot receive and supply required data and is kept in a waiting state, that is, in an operation suspended state.
Since the conventional microcomputer having a DRAM refresh function is structured as described above, the use of the data bus by the CPU for reading and writing data and the use of the data bus for refreshing the DRAM are determined by the arbitration of the bus arbiter, whereby the ON/OFF operations of the DRAM refresh controller and the bus interface control units are controlled. Therefore, arbitration takes an extremely long time. Furthermore, the DRAM refresh controller and the CPU each require an independent bus interface control unit and a bus arbiter, thus increasing the number of hardwares.